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Petri Net-Based Scheduling of Single-Arm Cluster Tools with Reentrant Atomic Layer Deposition Processes

Abstract : For some wafer fabrication processes in cluster tools, e.g., atomic layer deposition (ALD), wafer revisiting is required. Typically, in such processes, wafers need to visit two consecutive processing steps several times. Such a revisiting process can be denoted as (mi, mi + 1)h, where i means the ith-step and mi and mi + 1 mean the corresponding quantity of the processing modules in i and (i+1)th steps, and h the number of visiting times. This paper conducts a study for scheduling single-arm cluster tools with such a wafer revisiting process. The system is modeled by Petri nets (PNs) to guarantee the feasibility of robot activities. Based on the model, a deadlock avoidance policy is presented. With the control policy, cycle time analysis for the revisiting process is made. With the fact that wafer processing times are much longer than robot movement times in cluster tools, it is shown that, when mi = mi + 1 = 1, i.e., each step has only one processing module, the optimal one-wafer cyclic schedule is deterministic and unique, and the minimal cycle time can be calculated by an analytical expression. It is also shown that, when mi = 1 and mi + 1 = 2 or mi = 2 and mi + 1 = 1, the optimal one-wafer cyclic schedule can be obtained by finding h deterministic schedules and the one with the least cycle time. A novel analytical method is finally presented to schedule the overall system containing such reentrant wafer flow. This represents a significant advance in single-arm cluster equipment automation.
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https://hal.archives-ouvertes.fr/hal-00645145
Contributor : Frédéric Davesne <>
Submitted on : Saturday, November 26, 2011 - 6:48:47 PM
Last modification on : Tuesday, June 30, 2020 - 11:56:07 AM

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Naiqi Wu, Feng Chu, Chengbin Chu, Mengchu Zhou. Petri Net-Based Scheduling of Single-Arm Cluster Tools with Reentrant Atomic Layer Deposition Processes. IEEE Transactions on Automation Science and Engineering, Institute of Electrical and Electronics Engineers, 2011, 8 (1), pp.42--55. ⟨10.1109/TASE.2010.2046736⟩. ⟨hal-00645145⟩

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